A Framework for Area-Efficient Concurrent Online Checkers Design

This paper proposes a framework for automated evaluation and minimization of concurrent online checkers, with the aim of both achieving minimal fault detection latency, while at the same time maintaining the fault detection capabilities and keeping area consumption within the acceptable range. The proposed framework can be utilized for any digital circuit, however, our focus in this work as a case study is applying the framework to the control part of a Network-on-Chip router consisting of the routing computation and arbitration units. The novelty of the framework is its ability to formally prove the presence or absence of true misses. Experiments are performed both regarding the latency and the fault coverage of the checkers devised by the framework which indicate 100% fault coverage with acceptable area overhead and also instant (one cycle) detection of faults in the control part of a NoC router. Keywords— Network-on-Chip, routing logic, arbitration, concurrent online checking.